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ICCAD
2000
IEEE
74views Hardware» more  ICCAD 2000»
15 years 11 months ago
Simultaneous Gate Sizing and Fanout Optimization
This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the timing-critical paths in a circuit. First, a continuous-variable delay model that ...
Wei Chen, Cheng-Ta Hsieh, Massoud Pedram
VISUALIZATION
1998
IEEE
15 years 11 months ago
Progressive tetrahedralizations
This paper describes some fundamental issues for robust implementations of progressively refined tetrahedralizations generated through sequences of edge collapses. We address the ...
Oliver G. Staadt, Markus H. Gross
ADVIS
2004
Springer
15 years 11 months ago
On Families of New Adaptive Compression Algorithms Suitable for Time-Varying Source Data
In this paper, we introduce a new approach to adaptive coding which utilizes Stochastic Learning-based Weak Estimation (SLWE) techniques to adaptively update the probabilities of t...
Luís G. Rueda, B. John Oommen
CATA
2010
15 years 7 months ago
A Hardware Implementation of the Advanced Encryption Standard (AES) Algorithm using SystemVerilog
In this paper, a hardware implementation of the AES128 encryption algorithm is proposed. A unique feature of the proposed pipelined design is that the round keys, which are consum...
Bahram Hakhamaneshi, Behnam S. Arad
IEICET
2008
57views more  IEICET 2008»
15 years 7 months ago
Impact of Well Edge Proximity Effect on Timing
This paper studies impact of the well edge proximity effect on digital circuit delay, based on model parameters extracted from test structures in an industrial 65nm wafer process. ...
Toshiki Kanamoto, Yasuhiro Ogasahara, Keiko Natsum...