186 search results - page 22 / 38 » 1995 high level synthesis design repository |
190
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ISLPED
2003
ACM
16 years 3 hour ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
186
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ICCAD
2001
IEEE
16 years 3 months ago
2001
IEEE
: This paper describes ASF, a novel cell-level analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufactu...
205
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ICCAD
1995
IEEE
15 years 10 months ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
180
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CEC
2008
IEEE
16 years 1 months ago
2008
IEEE
— The high-level synthesis process involves three interdependent and NP-complete optimization problems: (i) the operation scheduling, (ii) the resource allocation, and (iii) the ...
161
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DATE
2003
IEEE
16 years 1 days ago
2003
IEEE
The ForSyDe methodology has been developed for system level design. Starting with a formal specification model, that captures the functionality of the system at a high abstractio...