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ANCS
2007
ACM
15 years 10 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos
CASES
2008
ACM
15 years 8 months ago
Multi-granularity sampling for simulating concurrent heterogeneous applications
Detailed or cycle-accurate/bit-accurate (CABA) simulation is a critical phase in the design flow of embedded systems. However, with increasing system complexity, full detailed sim...
Melhem Tawk, Khaled Z. Ibrahim, Smaïl Niar
PPOPP
2010
ACM
16 years 1 months ago
Thread to strand binding of parallel network applications in massive multi-threaded systems
In processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a singl...
Petar Radojkovic, Vladimir Cakarevic, Javier Verd&...
SECON
2007
IEEE
16 years 26 days ago
A SoC-based Sensor Node: Evaluation of RETOS-enabled CC2430
—Recent progress in Wireless Sensor Networks technology has enabled many complicated real-world applications. Some of the applications demand a non-trivial amount of computation;...
Sukwon Choi, Hojung Cha, SungChil Cho
ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
15 years 11 months ago
A case for FAME: FPGA architecture model execution
Given the multicore microprocessor revolution, we argue that the architecture research community needs a dramatic increase in simulation capacity. We believe FPGA Architecture Mod...
Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bi...