68 search results - page 1 / 14 » A Configuration Concept for a Massively Parallel FPGA Archit... |
164
Voted
CDES
2006
15 years 7 months ago
2006
201
Voted
JSA
2010
15 years 1 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
200
Voted
FPL
2010
Springer
15 years 4 months ago
2010
Springer
Significant advances in the field of configurable computing have enabled parallel processing within a single FieldProgrammable Gate Array (FPGA) chip. This paper presents the imple...
142
Voted
IPPS
2008
IEEE
16 years 23 days ago
2008
IEEE
168
Voted
ISCAS
2007
IEEE
16 years 20 days ago
2007
IEEE
— Increasing demands for robust image recognition systems require vision processors not only with enormous computational capacities but also with sufficient flexibility to hand...