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» A Framework for Scheduler Synthesis
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ISSS
1998
IEEE
96views Hardware» more  ISSS 1998»
15 years 11 months ago
Fine Grain Incremental Rescheduling Via Architectural Retiming
With the decreasing feature sizes during VLSI fabrication and the dominance of interconnect delay over that of gates, control logic and wiring no longer have a negligible impact o...
Soha Hassoun
DAC
1996
ACM
15 years 11 months ago
Issues and Answers in CAD Tool Interoperability
CAD tool interoperability issues are a recurring impediment to constructing a design methodology, especially if the methodology incorporates point tools from several vendors. Failu...
Mike Murray, Uwe B. Meding, Bill Berg, Yatin Trive...
VLSID
2010
IEEE
155views VLSI» more  VLSID 2010»
15 years 10 months ago
Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore
Abstract—Microfluidics-based biochips are revolutionizing highthroughput sequencing, parallel immunoassays, clinical diagnostics, and drug discovery. These devices enable the pre...
Krishnendu Chakrabarty
AAAI
1997
15 years 8 months ago
Using CSP Look-Back Techniques to Solve Real-World SAT Instances
We report on the performance of an enhanced version of the “Davis-Putnam” (DP) proof procedure for propositional satisfiability (SAT) on large instances derived from realworld...
Roberto J. Bayardo Jr., Robert Schrag
ICASSP
2009
IEEE
16 years 1 months ago
Exploiting statically schedulable regions in dataflow programs
Dataflow descriptions have been used in a wide range of Digital Signal Processing (DSP) applications, such as multi-media processing, and wireless communications. Among various f...
Ruirui Gu, Jörn W. Janneck, Mickaël Raul...