160 search results - page 26 / 32 » A General Buffer Scheme for the Windows Scheduling Problem |
186
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ICWN
2008
15 years 8 months ago
2008
In our previous work, a highly scalable and faulttolerant network architecture, the Progressive Multi-hop Rotational Clustered (PMRC) structure, is proposed for constructing large...
157
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USENIX
2000
15 years 7 months ago
2000
We examine a policy for managing modem pools that disconnects users only if not enough modems are available for other users to connect. Managing the modem pool then becomes a repl...
175
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IPPS
2003
IEEE
15 years 11 months ago
2003
IEEE
With the current trend in integration of more complex systems on chip there is a need for better communication infrastructure on chip that will increase the available bandwidth an...
166
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HPCA
2007
IEEE
16 years 6 months ago
2007
IEEE
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both laten...
288
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ISCA
2011
IEEE
14 years 10 months ago
2011
IEEE
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...