1998 search results - page 300 / 400 » A Hardware Implementation of PRAM and Its Performance Evalua... |
187
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RECONFIG
2009
IEEE
16 years 1 months ago
2009
IEEE
Abstract—The main challenge when implementing cryptographic algorithms in hardware is to protect them against attacks that target directly the device. Two strategies are customar...
181
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ICCAD
2002
IEEE
16 years 3 months ago
2002
IEEE
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
173
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ISCA
2007
IEEE
16 years 1 months ago
2007
IEEE
Conventional load/store queues (LSQs) are an impediment to both power-efficient execution in superscalar processors and scaling to large-window designs. In this paper, we propose...
162
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MICRO
2006
IEEE
16 years 26 days ago
2006
IEEE
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
168
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WORDS
2003
IEEE
16 years 3 days ago
2003
IEEE
The ’Distributed Control Lab’ [6] at Hasso-PlattnerInstitute, University of Potsdam allows experimentation with a variety of physical equipment via the web (intra and internet...