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191
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DATE
2009
IEEE
145views Hardware» more  DATE 2009»
16 years 2 months ago
Joint logic restructuring and pin reordering against NBTI-induced performance degradation
Negative Bias Temperature Instability (NBTI), a PMOS aging phenomenon causing significant loss on circuit performance and lifetime, has become a critical challenge for temporal re...
Kai-Chiang Wu, Diana Marculescu
209
Voted
FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
16 years 1 months ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier
CSFW
2003
IEEE
16 years 23 days ago
Understanding SPKI/SDSI Using First-Order Logic
SPKI/SDSI is a language for expressing distributed access control policy, derived from SPKI and SDSI. We provide a first-order logic (FOL) semantics for SDSI, and show that it ha...
Ninghui Li, John C. Mitchell
164
Voted
KBSE
2003
IEEE
16 years 22 days ago
On the automatic evolution of an OS kernel using temporal logic and AOP
Automating software evolution requires both identifying precisely the affected program points and selecting the appropriate modification at each point. This task is particularly ...
Rickard A. Åberg, Julia L. Lawall, Mario S&u...
IPPS
2000
IEEE
15 years 12 months ago
Study of a Multilevel Approach to Partitioning for Parallel Logic Simulation
Parallel simulation techniques are often employed to meet the computational requirements of large hardware simulations in order to reduce simulation time. In addition, partitionin...
Swaminathan Subramanian, Dhananjai Madhava Rao, Ph...