Sciweavers

1410 search results - page 29 / 282
» A Logic for Virtual Memory
Sort
View
TCAD
2008
115views more  TCAD 2008»
15 years 6 months ago
Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories
Abstract--The fabrication of crossbar memories with sublithographic features is expected to be feasible within several emerging technologies; in all of them, the nanowire (NW) deco...
M. Haykel Ben Jamaa, Kirsten E. Moselund, David At...
FCCM
2004
IEEE
141views VLSI» more  FCCM 2004»
15 years 10 months ago
Deep Packet Filter with Dedicated Logic and Read Only Memories
Searching for multiple string patterns in a stream of data is a computationally expensive task. The speed of the search pattern module determines the overall performance of deep p...
Young H. Cho, William H. Mangione-Smith
ICCAD
2007
IEEE
92views Hardware» more  ICCAD 2007»
16 years 3 months ago
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays
Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we sug...
M. Haykel Ben Jamaa, Kirsten E. Moselund, David At...
FPL
2000
Springer
119views Hardware» more  FPL 2000»
15 years 10 months ago
A Self-Reconfigurable Gate Array Architecture
Abstract. This paper presents an innovative architecture for a reconfigurable device that allows single cycle context switching and single cycle random access to the unified on-chi...
Reetinder P. S. Sidhu, Sameer Wadhwa, Alessandro M...
ASPDAC
2006
ACM
116views Hardware» more  ASPDAC 2006»
16 years 15 days ago
Abridged addressing: a low power memory addressing strategy
Abstract— The memory subsystem is known to comprise a significant fraction of the power dissipation in embedded systems. The memory addressing strategy, which determines the seq...
Preeti Ranjan Panda