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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
16 years 10 days ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
CLUSTER
2002
IEEE
16 years 6 days ago
User-Level Remote Data Access in Overlay Metacomputers
A practical problem faced by users of metacomputers and computational grids is: If my computation can move from one system to another, how can I ensure that my data will still be ...
Jeff Siegel, Paul Lu
ICPR
2002
IEEE
16 years 5 days ago
Biometric Hash based on Statistical Features of Online Signatures
This paper presents a new approach to generate biometric hash values based on statistical features in online signature signals. Whilst the output of typical online signature verif...
Claus Vielhauer, Ralf Steinmetz, Astrid Mayerh&oum...
INFOCOM
2002
IEEE
16 years 5 days ago
Scalable IP Lookup for Programmable Routers
Abstract— Continuing growth in optical link speeds places increasing demands on the performance of Internet routers, while deployment of embedded and distributed network services...
David E. Taylor, John W. Lockwood, Todd S. Sproull...
ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
16 years 5 days ago
Tarantula: A Vector Extension to the Alpha Architecture
Tarantula is an aggressive floating point machine targeted at technical, scientific and bioinformatics workloads, originally planned as a follow-on candidate to the EV8 processo...
Roger Espasa, Federico Ardanaz, Julio Gago, Roger ...
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