522 search results - page 98 / 105 » A Note on Designing Logical Circuits Using SAT |
156
Voted
DAC
2005
ACM
16 years 7 months ago
2005
ACM
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
168
Voted
DATE
2007
IEEE
16 years 21 days ago
2007
IEEE
This paper introduces a method and tool-support for the automatic analysis and verification of hybrid and embedded control systems, whose continuous dynamics are often modelled u...
145
Voted
GLVLSI
2009
IEEE
16 years 1 months ago
2009
IEEE
In the context of formal verification Bounded Model Checking (BMC) has shown to be very powerful for large industrial designs. BMC is used to check whether a circuit satisfies a...
152
Voted
DATE
2007
IEEE
16 years 21 days ago
2007
IEEE
The ability to guarantee the functional correctness of digital integrated circuits and, in particular, complex microprocessors, is a key task in the production of secure and trust...
147
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CF
2006
ACM
16 years 10 days ago
2006
ACM
In this paper, we present a nano-scale reconfigurable mesh that is interconnected with ferromagnetic spin-wave buses. The architecture described here, while requiring the same num...