Sciweavers

11374 search results - page 1942 / 2275
» A System Demonstration of ST-TCP
Sort
View
ICCD
2008
IEEE
420views Hardware» more  ICCD 2008»
16 years 4 months ago
Frequency and voltage planning for multi-core processors under thermal constraints
— Clock frequency and transistor density increases have resulted in elevated chip temperatures. In order to meet temperature constraints while still exploiting the performance op...
Michael Kadin, Sherief Reda
ASPLOS
2010
ACM
16 years 2 months ago
Speculative parallelization using software multi-threaded transactions
With the right techniques, multicore architectures may be able to continue the exponential performance trend that elevated the performance of applications of all types for decades...
Arun Raman, Hanjun Kim, Thomas R. Mason, Thomas B....
CHI
2010
ACM
16 years 2 months ago
LayerPaint: a multi-layer interactive 3D painting interface
Painting on 3D surfaces is an important operation in computer graphics, virtual reality, and computer aided design. The painting styles in existing WYSIWYG systems can be awkward,...
Chi-Wing Fu, Jiazhi Xia, Ying He 0001
199
Voted
LCTRTS
2010
Springer
16 years 2 months ago
Operation and data mapping for CGRAs with multi-bank memory
Coarse Grain Reconfigurable Architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and movi...
Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Yunh...
199
Voted
ISPASS
2009
IEEE
16 years 2 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
« Prev « First page 1942 / 2275 Last » Next »