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DAC
2007
ACM
16 years 8 months ago
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
DAC
2001
ACM
16 years 8 months ago
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshmi...
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DAC
2002
ACM
16 years 8 months ago
A universal technique for fast and flexible instruction-set architecture simulation
In the last decade, instruction-set simulators have become an essential development tool for the design of new programmable architectures. Consequently, the simulator performance ...
Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rain...
DAC
2004
ACM
16 years 8 months ago
A novel approach for flexible and consistent ADL-driven ASIP design
Architecture description languages (ADL) have been established to aid the design of application-specific instruction-set processors (ASIP). Their main contribution is the automati...
Achim Nohl, Gunnar Braun, Hanno Scharwächter,...
DAC
2004
ACM
16 years 8 months ago
A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits
Circuits using nano-meter technologies are becoming increasingly vulnerable to signal interference from multiple noise sources as well as radiation-induced soft errors. One way to...
Chong Zhao, Xiaoliang Bai, Sujit Dey
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