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» A Technique for Invariant Generation
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DAC
2003
ACM
16 years 16 days ago
Test generation for designs with multiple clocks
To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize ...
Xijiang Lin, Rob Thompson
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
15 years 11 months ago
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
DATE
1997
IEEE
100views Hardware» more  DATE 1997»
15 years 11 months ago
On the generation of pseudo-deterministic two-patterns test sequence with LFSRs
Many Built-In Self Test pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs o...
Christian Dufaza, Yervant Zorian
DFT
1997
IEEE
108views VLSI» more  DFT 1997»
15 years 11 months ago
Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations
The paper presents a test pattern generation and fault simulation methodology for the detection of catastrophic faults in analogue circuits. The test methodology chosen for evalua...
Stephen J. Spinks, Chris D. Chalk, Ian M. Bell, Ma...
SACRYPT
1998
Springer
15 years 11 months ago
Computational Alternatives to Random Number Generators
In this paper, we present a simple method for generating random-based signatures when random number generators are either unavailable or of suspected quality (malicious or accident...
David M'Raïhi, David Naccache, David Pointche...