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» A Temporal Logic of Robustness
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ECML
2003
Springer
16 years 6 days ago
Robust k-DNF Learning via Inductive Belief Merging
A central issue in logical concept induction is the prospect of inconsistency. This problem may arise due to noise in the training data, or because the target concept does not fit...
Frédéric Koriche, Joël Quinquet...
197
Voted
TIME
2007
IEEE
16 years 1 months ago
A Symbolic Decision Procedure for Robust Safety of Timed Systems
We present a symbolic algorithm for deciding safety (reachability) of timed systems modelled as Timed Automata (TA), under the notion of robustness w.r.t. infinitesimal clock-drif...
Mani Swaminathan, Martin Fränzle
ISCAS
2002
IEEE
94views Hardware» more  ISCAS 2002»
15 years 12 months ago
A robust self-resetting CMOS 32-bit parallel adder
This paper presents new circuit configurationsfor a more robust and efficient form of self-resettingCMOS (SRCMOS). Prior structures for SRCMOS have very high performance but are...
Gunok Jung, V. A. Sundarajan, Gerald E. Sobelman
209
Voted
ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
16 years 3 months ago
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustne...
Mihir R. Choudhury, Quming Zhou, Kartik Mohanram
198
Voted
DDECS
2009
IEEE
106views Hardware» more  DDECS 2009»
16 years 1 months ago
Forward and backward guarding in early output logic
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
Charlie Brej, Doug Edwards