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FPL
2009
Springer
172views Hardware» more  FPL 2009»
16 years 7 days ago
Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor...
Nachiket Kapre, André DeHon
ISCA
2010
IEEE
247views Hardware» more  ISCA 2010»
15 years 11 months ago
An integrated GPU power and performance model
GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Performance optimization for multi-core processors has been a c...
Sunpyo Hong, Hyesoon Kim
ASPDAC
2005
ACM
111views Hardware» more  ASPDAC 2005»
15 years 9 months ago
Wave-pipelined on-chip global interconnect
— A novel wave-pipelined global interconnect system is developed for reliable, high throughput, on-chip data communication. We argue that because there is only a single signal pr...
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
JMLR
2010
106views more  JMLR 2010»
15 years 2 months ago
Why Does Unsupervised Pre-training Help Deep Learning?
Much recent research has been devoted to learning algorithms for deep architectures such as Deep Belief Networks and stacks of auto-encoder variants, with impressive results obtai...
Dumitru Erhan, Yoshua Bengio, Aaron C. Courville, ...
MJ
2007
119views more  MJ 2007»
15 years 7 months ago
Automated energy calculation and estimation for delay-insensitive digital circuits
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...
Venkat Satagopan, Bonita Bhaskaran, Anshul Singh, ...