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MICRO
2010
IEEE
167views Hardware» more  MICRO 2010»
15 years 5 months ago
Erasing Core Boundaries for Robust and Configurable Performance
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address thes...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott ...
DSN
2007
IEEE
16 years 1 months ago
Web Services Wind Tunnel: On Performance Testing Large-Scale Stateful Web Services
New versions of existing large-scale web services such as Passport.com© have to go through rigorous performance evaluations in order to ensure a high degree of availability. Perf...
Marcelo De Barros, Jing Shiau, Chen Shang, Kenton ...
RECONFIG
2008
IEEE
225views VLSI» more  RECONFIG 2008»
16 years 1 months ago
A Hardware Filesystem Implementation for High-Speed Secondary Storage
Platform FPGAs are capable of hosting entire Linuxbased systems including standard peripherals, integrated network interface cards and even disk controllers on a single chip. File...
Ashwin A. Mendon, Ron Sass
246
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RTAS
1997
IEEE
15 years 11 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
TRECVID
2008
15 years 8 months ago
Learning TRECVID'08 High-Level Features from YouTube
Run No. Run ID Run Description infMAP (%) training on TV08 data 1 IUPR-TV-M SIFT visual words with maximum entropy 6.1 2 IUPR-TV-MF SIFT with maximum entropy, fused with color+tex...
Adrian Ulges, Christian Schulze, Markus Koch, Thom...