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TCSV
2008
225views more  TCSV 2008»
15 years 7 months ago
Analysis and Efficient Architecture Design for VC-1 Overlap Smoothing and In-Loop Deblocking Filter
Abstract--In contrast to the macroblock-based in-loop deblocking filters, the filters of VC-1 perform all horizontal edges (for in-loop filtering) or vertical edges (for overlap sm...
Yen-Lin Lee, T. Q. Nguyen
SOSP
2001
ACM
16 years 4 months ago
SEDA: An Architecture for Well-Conditioned, Scalable Internet Services
We propose a new design for highly concurrent Internet services, which we call the staged event-driven architecture (SEDA). SEDA is intended to support massive concurrency demands...
Matt Welsh, David E. Culler, Eric A. Brewer
SASP
2008
IEEE
153views Hardware» more  SASP 2008»
16 years 1 months ago
TRaX: A Multi-Threaded Architecture for Real-Time Ray Tracing
Ray tracing is a technique used for generating highly realistic computer graphics images. In this paper, we explore the design of a simple but extremely parallel, multi-threaded, ...
Josef B. Spjut, Solomon Boulos, Daniel Kopta, Erik...
CASES
2001
ACM
15 years 10 months ago
A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture
The rapid growth of silicon densities has made it feasible to deploy reconfigurable hardware as a highly parallel computing platform. However, in most cases, the application needs...
Girish Venkataramani, Walid A. Najjar, Fadi J. Kur...
ASPDAC
2008
ACM
94views Hardware» more  ASPDAC 2008»
15 years 9 months ago
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival
A major trend in a modern system-on-chip design is a growing system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architec...
Sujan Pandey, Rolf Drechsler