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» A high performance JPEG2000 architecture
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TIP
2008
175views more  TIP 2008»
15 years 7 months ago
Algorithmic and Architectural Optimizations for Computationally Efficient Particle Filtering
Abstract--In this paper, we analyze the computational challenges in implementing particle filtering, especially to video sequences. Particle filtering is a technique used for filte...
Aswin C. Sankaranarayanan, Ankur Srivastava, Rama ...
HPDC
2008
IEEE
16 years 1 months ago
Harmony: an execution model and runtime for heterogeneous many core systems
The emergence of heterogeneous many core architectures presents a unique opportunity for delivering order of magnitude performance increases to high performance applications by ma...
Gregory F. Diamos, Sudhakar Yalamanchili
ASPDAC
2006
ACM
143views Hardware» more  ASPDAC 2006»
16 years 1 months ago
Constraint-driven bus matrix synthesis for MPSoC
– Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based com...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
ANCS
2005
ACM
16 years 22 days ago
High-throughput linked-pattern matching for intrusion detection systems
This paper presents a hardware architecture for highly efficient intrusion detection systems. In addition, a software tool for automatically generating the hardware is presented....
Zachary K. Baker, Viktor K. Prasanna
ISPA
2007
Springer
16 years 1 months ago
Parallelization Strategies for the Points of Interests Algorithm on the Cell Processor
The Cell processor is a typical example of a heterogeneous multiprocessor-on-chip architecture that uses several levels of parallelism to deliver high performance. Closing the gap ...
Tarik Saidani, Lionel Lacassagne, Samir Bouaziz, T...