315 search results - page 47 / 63 » A low complexity hardware architecture for motion estimation |
188
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HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
In future multi-cores, large amounts of delay and power will be spent accessing data in large L2/L3 caches. It has been recently shown that OS-based page coloring allows a non-uni...
179
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ICCD
2007
IEEE
16 years 3 months ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
168
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ASAP
2006
IEEE
15 years 8 months ago
2006
IEEE
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
158
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ACSAC
2006
IEEE
16 years 20 days ago
2006
IEEE
We propose an architecture of four complimentary technologies increasingly relevant to a growing number of home users and organizations: cryptography, separation kernels, formal v...
164
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ICIP
2007
IEEE
16 years 8 months ago
2007
IEEE
We propose a method for delivering error-resilient video from wireless camera networks in a distributed fashion over lossy channels. Our scheme is based on distributed source codi...