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TCAD
1998
127views more  TCAD 1998»
15 years 6 months ago
Gate-level power estimation using tagged probabilistic simulation
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the noti...
Chih-Shun Ding, Chi-Ying Tsui, Massoud Pedram
IJHCI
2010
144views more  IJHCI 2010»
15 years 5 months ago
Naturalistic Decision Making for Power System Operators
Motivation – Investigations of large-scale outages in the North American interconnected electric system often attribute the causes to three T’s: Trees, Training and Tools. To ...
Frank L. Greitzer, Robin Podmore, Marck Robinson, ...
DAC
1999
ACM
16 years 8 months ago
Converting a 64b PowerPC Processor from CMOS Bulk to SOI Technology
A 550MHz 64b PowerPC processor was developed for fabrication in Silicon-On-Insulator (SOI) technology from a processor previously designed and fabricated in bulk CMOS [1]. Both th...
D. Allen, D. Behrends, B. Stanisic
WOWMOM
2006
ACM
130views Multimedia» more  WOWMOM 2006»
16 years 29 days ago
Power Control in Multihop CSMA
—This paper aims at improving the power efficiency of the CSMA/CA protocol for transmission of multimedia information over multihop wireless channels. Using a distance dependent ...
Bo Yan, Hamid Gharavi
ASPDAC
2005
ACM
87views Hardware» more  ASPDAC 2005»
16 years 17 days ago
Static power minimization in current-mode circuits
-We propose a method involvingselectivesignalgating to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current ...
M. S. Bhat, H. S. Jamadagni