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SOCC
2008
IEEE
151views Education» more  SOCC 2008»
16 years 1 months ago
Failure analysis for ultra low power nano-CMOS SRAM under process variations
— Several design metrics have been used in the past to evaluate the SRAM cell stability. However, most of them fail to provide the exact stability figures as shown in this paper...
Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Sar...
ICMCS
2007
IEEE
107views Multimedia» more  ICMCS 2007»
16 years 1 months ago
Power Efficient Motion Estimation using Multiple Imprecise Metric Computations
In this paper, we propose power efficient motion estimation (ME) using multiple imprecise sum absolute difference (SAD) metric computations. We extend recent work in [18] by prov...
In Suk Chong, Antonio Ortega
VTC
2007
IEEE
16 years 1 months ago
Power Optimization of IDMA Systems with Different Target BER Constraints
— Interleave Division Multiple Access (IDMA) is a promising air interface for future wireless networks. Optimization of access schemes regarding cross user aspects is also a topi...
Petra Weitkemper, Karl-Dirk Kammeyer
ISVLSI
2005
IEEE
129views VLSI» more  ISVLSI 2005»
16 years 21 days ago
Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits
— Direct tunneling current is the major component of static power dissipation of a CMOS circuit for technology below 65nm, where the gate dielectric (SiO2) is very low. We intuit...
Saraju P. Mohanty, Ramakrishna Velagapudi, Valmiki...
ISLPED
2004
ACM
122views Hardware» more  ISLPED 2004»
16 years 16 days ago
Microarchitectural techniques for power gating of execution units
Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-...
Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan,...