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ASPDAC
2006
ACM
157views Hardware» more  ASPDAC 2006»
16 years 1 months ago
Delay modeling and static timing analysis for MTCMOS circuits
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
Naoaki Ohkubo, Kimiyoshi Usami
DAC
2002
ACM
16 years 8 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
DAC
2005
ACM
16 years 8 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
INFOCOM
2007
IEEE
16 years 1 months ago
QoS-Driven Power Allocation Over Parallel Fading Channels With Imperfect Channel Estimations in Wireless Networks
— We propose the quality-of-service (QoS) driven power allocation schemes for parallel fading channels when considering imperfect channel estimations. In particular, the parallel...
Jia Tang, Xi Zhang
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
16 years 13 days ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...