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JCNS
1998
139views more  JCNS 1998»
15 years 7 months ago
Competitive Calcium Binding: Implications for Dendritic Calcium Signaling
Action potentials evoke calcium transients in dendrites of neocortical pyramidal neurons with time constants of <100 ms at physiological temperature. This time period may not be...
Henry Markram, Arnd Roth, Fritjof Helmchen
JUCS
2002
116views more  JUCS 2002»
15 years 7 months ago
Bounded Flooding Routing Algorithm for Provisioning the Globally Optimal Route in a Hierarchical ATM Network
: ATM virtual path (VP) contains bundles of virtual channels (VCs). A VP layer network can be used as a server layer network of VC layer networks and each VC layer network can be a...
Daniel Won-Kyu Hong, Choong Seon Hong, Dong-Sik Yu...
JISE
1998
84views more  JISE 1998»
15 years 7 months ago
Determining the Idle Time of a Tiling: New Results
In the framework of perfect loop nests with uniform dependences, tiling has been extensively studied as a source-to-source program transformation. We build upon recent results by ...
Frederic Desprez, Jack Dongarra, Fabrice Rastello,...
194
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MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
15 years 7 months ago
Generating physical addresses directly for saving instruction TLB energy
Power consumption and power density for the Translation Lookaside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as w...
Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. K...
205
Voted
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
15 years 7 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
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