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MICRO
2010
IEEE
202views Hardware» more  MICRO 2010»
15 years 1 months ago
Hardware Support for Relaxed Concurrency Control in Transactional Memory
Today's transactional memory systems implement the two-phase-locking (2PL) algorithm which aborts transactions every time a conflict happens. 2PL is a simple algorithm that pr...
Utku Aydonat, Tarek S. Abdelrahman
APGV
2010
ACM
236views Visualization» more  APGV 2010»
15 years 10 months ago
The effect of stereo and context on memory and awareness states in immersive virtual environments
Spatial awareness is crucial for human performance efficiency of any task that entails perception of space. Memory of spaces is an imperfect reflection of the cognitive activity (...
Adam Bennett, Matthew Coxon, Katerina Mania
ISCA
2006
IEEE
125views Hardware» more  ISCA 2006»
16 years 1 months ago
Architectural Semantics for Practical Transactional Memory
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
Austen McDonald, JaeWoong Chung, Brian D. Carlstro...
HPCA
1998
IEEE
15 years 11 months ago
PRISM: An Integrated Architecture for Scalable Shared Memory
This paper describes PRISM, a distributed sharedmemory architecture that relies on a tightly integrated hardware and operating system design for scalable and reliable performance....
Kattamuri Ekanadham, Beng-Hong Lim, Pratap Pattnai...
221
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SOSP
1997
ACM
15 years 8 months ago
Towards Transparent and Efficient Software Distributed Shared Memory
Despite a large research effort, software distributed shared memory systems have not been widely used to run parallel applications across clusters of computers. The higher perform...
Daniel J. Scales, Kourosh Gharachorloo