3865 search results - page 183 / 773 » Active memory operations |
171
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TVLSI
2002
15 years 6 months ago
2002
This paper presents an irredundant encoding technique to minimize the switching activity on a multiplexed Dynamic RAM (DRAM) address bus. The DRAM switching activity can be classif...
187
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ISCA
2009
IEEE
16 years 1 months ago
2009
IEEE
Data prefetching has long been an important technique to amortize the effects of the memory wall, and is likely to remain so in the current era of multi-core systems. Most prefetc...
189
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PVM
2009
Springer
16 years 1 months ago
2009
Springer
Abstract. Most parallel systems on which MPI is used are now hierarchical: some processors are much closer to others in terms of interconnect performance. One of the most common su...
201
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ISCA
2008
IEEE
16 years 1 months ago
2008
IEEE
Efficiently utilizing off-chip DRAM bandwidth is a critical issue in designing cost-effective, high-performance chip multiprocessors (CMPs). Conventional memory controllers deli...
198
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DATE
2007
IEEE
16 years 1 months ago
2007
IEEE
Chip-multiprocessors are quickly becoming popular in embedded systems. However, the practical success of CMPs strongly depends on addressing the difficulty of multithreaded appli...