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FCCM
2004
IEEE
118views VLSI» more  FCCM 2004»
15 years 11 months ago
Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor
Reconfigurable System-on-Chip (SoC) platforms that incorporate hard-core processors surrounded by large amounts of FPGA are today commodities: the reconfigurable logic is often us...
Miljan Vuletic, Laura Pozzi, Paolo Ienne
ISCA
2011
IEEE
290views Hardware» more  ISCA 2011»
14 years 11 months ago
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks
To meet the demand for more powerful high-performance shared-memory servers, multiprocessor systems must incorporate efficient and scalable cache coherence protocols, such as thos...
Blas Cuesta, Alberto Ros, María Engracia G&...
SIGMOD
2009
ACM
213views Database» more  SIGMOD 2009»
16 years 7 months ago
Dictionary-based order-preserving string compression for main memory column stores
Column-oriented database systems [19, 23] perform better than traditional row-oriented database systems on analytical workloads such as those found in decision support and busines...
Carsten Binnig, Stefan Hildenbrand, Franz Fär...
ISCA
2007
IEEE
174views Hardware» more  ISCA 2007»
16 years 1 months ago
An integrated hardware-software approach to flexible transactional memory
There has been considerable recent interest in the support of transactional memory (TM) in both hardware and software. We present an intermediate approach, in which hardware is us...
Arrvindh Shriraman, Michael F. Spear, Hemayet Hoss...
MASCOTS
2010
15 years 8 months ago
PUD-LRU: An Erase-Efficient Write Buffer Management Algorithm for Flash Memory SSD
Flash memory SSDs pose a well-known challenge, that is, the erase-before-write problem. Researchers try to solve this inherent problem from two different angles by either designing...
Jian Hu, Hong Jiang, Lei Tian, Lei Xu