3865 search results - page 248 / 773 » Active memory operations |
195
click to vote
HPCA
1996
IEEE
15 years 11 months ago
1996
IEEE
Traditional DMA requires the operating system to perform many tasks to initiate a transfer, with overhead on the order of hundreds or thousands of CPU instructions. This paper des...
188
click to vote
IOLTS
2008
IEEE
16 years 1 months ago
2008
IEEE
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
158
click to vote
CASSIS
2005
Springer
16 years 23 days ago
2005
Springer
Memory is one of the scarcest resource of embedded and constrained devices. This paper studies the memory footprint benefit of pre-deploying embedded Java systems up to their acti...
206
click to vote
ICS
2009
Tsinghua U.
16 years 2 months ago
2009
Tsinghua U.
The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has...
216
click to vote
ICPP
2008
IEEE
16 years 1 months ago
2008
IEEE
An asynchronous work-stealing implementation of dynamic load balance is implemented using Unified Parallel C (UPC) and evaluated using the Unbalanced Tree Search (UTS) benchmark ...