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SOCC
2008
IEEE
169views Education» more  SOCC 2008»
16 years 1 months ago
A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies
— Lowering supply voltage is an effective technique for power reduction in memory design, however traditional memory cell design fails to operate, as shown in [3], [10], at ultra...
Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Sar...
SRDS
2007
IEEE
16 years 1 months ago
Distributed Software-based Attestation for Node Compromise Detection in Sensor Networks
Sensors that operate in an unattended, harsh or hostile environment are vulnerable to compromises because their low costs preclude the use of expensive tamper-resistant hardware. ...
Yi Yang, Xinran Wang, Sencun Zhu, Guohong Cao
ASPDAC
2006
ACM
140views Hardware» more  ASPDAC 2006»
16 years 1 months ago
A near optimal deblocking filter for H.264 advanced video coding
- We propose a near optimal hardware architecture for deblocking filter in H.264/MPEG-4 AVC. We propose a novel filtering order and a data reuse strategy that result in significant...
Shen-Yu Shih, Cheng-Ru Chang, Youn-Long Lin
ISNN
2005
Springer
16 years 23 days ago
A SIMD Neural Network Processor for Image Processing
Abstract. Artificial Neural Networks (ANNs) and image processing requires massively parallel computation of simple operator accompanied by heavy memory access. Thus, this type of ...
Dongsun Kim, Hyunsik Kim, Hongsik Kim, Gunhee Han,...
MICRO
1997
IEEE
79views Hardware» more  MICRO 1997»
15 years 11 months ago
On High-Bandwidth Data Cache Design for Multi-Issue Processors
Highly aggressive multi-issue processor designs of the past few years and projections for the next decade require that we redesign the operation of the cache memory system. The nu...
Jude A. Rivers, Gary S. Tyson, Edward S. Davidson,...