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186
Voted
ICA3PP
2009
Springer
16 years 1 days ago
2009
Springer
Abstract. Practical implementations of atomically consistent read/write memory service are important building blocks for higher level applications. This is especially true when dat...
175
Voted
MICRO
1998
IEEE
15 years 11 months ago
1998
IEEE
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our...
253
Voted
SIGMETRICS
1996
ACM
15 years 11 months ago
1996
ACM
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simul...
238
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ICS
2010
Tsinghua U.
15 years 10 months ago
2010
Tsinghua U.
The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have ...
243
click to vote
IEEEPACT
2009
IEEE
15 years 5 months ago
2009
IEEE
Transactional memory is being advanced as an alternative to traditional lock-based synchronization for concurrent programming. Transactional memory simplifies the programming mode...