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IPPS
2009
IEEE
16 years 2 months ago
Designing multi-leader-based Allgather algorithms for multi-core clusters
The increasing demand for computational cycles is being met by the use of multi-core processors. Having large number of cores per node necessitates multi-core aware designs to ext...
Krishna Chaitanya Kandalla, Hari Subramoni, Gopala...
DATE
2007
IEEE
124views Hardware» more  DATE 2007»
16 years 1 months ago
Worst-case design and margin for embedded SRAM
An important aspect of Design for Yield for embedded SRAM is identifying the expected worst case behavior in order to guarantee that sufficient design margin is present. Previousl...
Robert C. Aitken, Sachin Idgunji
DDECS
2007
IEEE
93views Hardware» more  DDECS 2007»
16 years 1 months ago
Manifestation of Precharge Faults in High Speed DRAM Devices
Abstract: High speed DRAMs today suffer from an increased sensitivity to interference and noise problems. Signal integrity issues, caused by bit line and word line coupling, result...
Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev
186
Voted
MIDDLEWARE
2007
Springer
16 years 1 months ago
XenSocket: A High-Throughput Interdomain Transport for Virtual Machines
This paper presents the design and implementation of XenSocket, a UNIX-domain-socket-like construct for high-throughput interdomain (VM-to-VM) communication on the same system. The...
Xiaolan Zhang, Suzanne McIntosh, Pankaj Rohatgi, J...
186
Voted
TACAS
2007
Springer
105views Algorithms» more  TACAS 2007»
16 years 1 months ago
Hoare Logic for Realistically Modelled Machine Code
This paper presents a mechanised Hoare-style programming logic framework for assembly level programs. The framework has been designed to fit on top of operational semantics of rea...
Magnus O. Myreen, Michael J. C. Gordon