Sciweavers

3865 search results - page 414 / 773
» Active memory operations
Sort
View
224
Voted
ISCAS
2002
IEEE
190views Hardware» more  ISCAS 2002»
16 years 17 days ago
A high performance JPEG2000 architecture
—JPEG2000 is an upcoming compression standard for still images that has a feature set well tuned for diverse data dissemination. These features are possible due to adaptation of ...
Kishore Andra, Chaitali Chakrabarti, Tinku Acharya
EUROPAR
2001
Springer
16 years 4 days ago
A Software Architecture for User Transparent Parallel Image Processing on MIMD Computers
Abstract. This paper describes a software architecture that allows image processing researchers to develop parallel applications in a transparent manner. The architecture’s main ...
Frank J. Seinstra, Dennis Koelma, Jan-Mark Geusebr...
EH
1999
IEEE
141views Hardware» more  EH 1999»
15 years 12 months ago
On-Line Evolution of FPGA-Based Circuits: A Case Study on Hash Functions
An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16bit address space into an 8-bit one. The target technology is FPGA,...
Ernesto Damiani, Andrea Tettamanzi, Valentino Libe...
HICSS
1999
IEEE
87views Biometrics» more  HICSS 1999»
15 years 12 months ago
Interfacing the MoM-PDA to an Internet-based Development System
The paper introduces an internet-based remote prototyping platform for accelerator applications. It gives an overview on the Xputer prototype Map-oriented Machine with Parallel Da...
Michael Herz, Thomas Hoffmann, Ulrich Nageldinger,...
IPPS
1999
IEEE
15 years 12 months ago
NWCache: Optimizing Disk Accesses via an Optical Network/Write Cache Hybrid
In this paper we propose a simple extension to the I/O architecture of scalable multiprocessors that optimizes page swap-outs significantly. More specifically, we propose the use o...
Enrique V. Carrera, Ricardo Bianchini