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243
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SASP
2009
IEEE
291views Hardware» more  SASP 2009»
16 years 2 months ago
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
Alexandros Papakonstantinou, Karthik Gururaj, John...
IISWC
2009
IEEE
16 years 2 months ago
Experimental evaluation of N-tier systems: Observation and analysis of multi-bottlenecks
In many areas such as e-commerce, mission-critical N-tier applications have grown increasingly complex. They are characterized by non-stationary workloads (e.g., peak load several...
Simon Malkowski, Markus Hedwig, Calton Pu
265
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EDOC
2008
IEEE
16 years 1 months ago
Facebook Meets the Virtualized Enterprise
: “Web 2.0” and “cloud computing” are revolutionizing the way IT infrastructure is accessed and managed. Web 2.0 technologies such as blogs, wikis and social networking pla...
Roger Curry, Cameron Kiddle, Nayden Markatchev, Ro...
HPDC
2007
IEEE
16 years 1 months ago
A fast topology inference: a building block for network-aware parallel processing
Adapting to the network is the key to achieving high performance for communication-intensive applications, including scientific computing, data intensive computing, and multicast...
Tatsuya Shirai, Hideo Saito, Kenjiro Taura
HIPEAC
2007
Springer
16 years 1 months ago
A Throughput-Driven Task Creation and Mapping for Network Processors
Abstract. Network processors are programmable devices that can process packets at a high speed. A network processor is typified by multithreading and heterogeneous multiprocessing...
Lixia Liu, Xiao-Feng Li, Michael K. Chen, Roy Dz-C...