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2005
Tsinghua U.
16 years 21 days ago
Reducing latencies of pipelined cache accesses through set prediction
With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...
Aneesh Aggarwal
HPDC
2003
IEEE
16 years 14 days ago
Optimizing GridFTP through Dynamic Right-Sizing
In this paper, we describe the integration of dynamic right-sizing — an automatic and scalable buffer management technique for enhancing TCP performance — into GridFTP, a sub...
Sunil Thulasidasan, Wu-chun Feng, Mark K. Gardner
ICNP
2003
IEEE
16 years 14 days ago
Data Dissemination with Ring-Based Index for Wireless Sensor Networks
In current sensor networks, sensor nodes are capable of not only measuring real world phenomena, but also storing, processing and transferring these measurements. Many data dissem...
Wensheng Zhang, Guohong Cao, Thomas F. La Porta
SENSYS
2003
ACM
16 years 13 days ago
DFuse: a framework for distributed data fusion
Simple in-network data aggregation (or fusion) techniques for sensor networks have been the focus of several recent research efforts, but they are insufficient to support advance...
Rajnish Kumar, Matthew Wolenetz, Bikash Agarwalla,...
GLVLSI
2010
IEEE
210views VLSI» more  GLVLSI 2010»
16 years 8 days ago
Overscaling-friendly timing speculation architectures
Processors have traditionally been designed for the worst-case, resulting in designs that have high yields, but are expensive in terms of area and power. Better-than-worst-case (B...
John Sartori, Rakesh Kumar