A cache line size has a signi cant e ect on missrate and memorytra c. Today's computers use a xed line size, typically 32B, which may not be optimalfor a given application. O...
Alexander V. Veidenbaum, Weiyu Tang, Rajesh K. Gup...
Heterogeneous network-based systems are emerging as attractive computing platforms for HPC applications. This paper discusses fundamental research issues that must be addressed to...
Prashanth B. Bhat, Viktor K. Prasanna, Cauligi S. ...
Recently, a real-time clustering microchip based on the ART1 algorithm has been reported. That chip was able to classify 100-bit input patterns into up to 18 categories. However, i...
Compressing real-time input through bandwidth constrained connections has been studied within robotics, wireless sensor networks, and image processing. When there are bandwidth con...
Dynamic optimization presents opportunities for finding run-time bottlenecks and deploying optimizations in statically compiled programs. In this paper, we discuss our current impl...
Howard Chen, Jiwei Lu, Wei-Chung Hsu, Pen-Chung Ye...