Abstract. A time-lock puzzle is a mechanism for sending messages “to the future”. The sender publishes a puzzle whose solution is the message to be sent, thus hiding it until e...
We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program ...
We present a case study about the application of the inductive database approach to the analysis of Web logs. We consider rich XML Web logs ? called conceptual logs ? that are gen...
Rosa Meo, Pier Luca Lanzi, Maristella Matera, Robe...
The analysis of gene expression time series obtained from microarray experiments can be effectively exploited to understand a wide range of biological phenomena from the homeostat...
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...