18306 search results - page 502 / 3662 » Algorithmics in Exponential Time |
223
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ICCD
2003
IEEE
16 years 4 months ago
2003
IEEE
This paper introduces a new method for two-level logic minimization. Unlike previous approaches, the new method uses a SAT solver as an underlying engine. While the overall minimi...
160
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DFT
2005
IEEE
16 years 1 months ago
2005
IEEE
In this paper, we present two novel methodologies for testing the interconnect fabrics of network-on-chip (NoC) based chips. Both use the concept of recursive testing, with differ...
142
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ICCAD
1999
IEEE
15 years 12 months ago
1999
IEEE
This paper presents a new solution for combining technology mapping with placement, coupling the two into one phase. The original aspects of our work are the use of libraryless ma...
169
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RSP
1999
IEEE
15 years 12 months ago
1999
IEEE
A platform and methodology for real time systems on chip prototyping is presented. The JPEG case study is presented as an example of prototyping. The proposed methodology overcome...
200
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SIAMCOMP
2008
15 years 7 months ago
2008
Helly's theorem says that, if every d+1 elements of a given finite set of convex objects in Rd have a common point, there is a point common to all of the objects in the set. I...