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RTCSA
2007
IEEE
16 years 1 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
ICPPW
2002
IEEE
16 years 15 days ago
A Statistical Approach for the Analysis of the Relation Between Low-Level Performance Information, the Code, and the Environment
This paper presents a methodology for aiding a scientific programmer to evaluate the performance of parallel programs on advanced architectures. It applies well-defined design o...
Nayda G. Santiago, Diane T. Rover, Domingo Rodr&ia...
FCCM
1997
IEEE
118views VLSI» more  FCCM 1997»
15 years 11 months ago
Computing kernels implemented with a wormhole RTR CCM
The Wormhole Run-Time Reconfiguration (RTR) computing paradigm is a method for creating high performance computational pipelines. The scalability, distributed control and data pow...
Ray Bittner, Peter M. Athanas
CCGRID
2006
IEEE
16 years 1 months ago
Calder Query Grid Service: Insights and Experimental Evaluation
We have architected and evaluated a new kind of data resource, one that is composed of a logical collection of ephemeral data streams that could be viewed as a collection of publi...
Nithya N. Vijayakumar, Ying Liu, Beth Plale
ICPPW
1999
IEEE
15 years 12 months ago
Multistage Ring Network: A New Multiple Ring Network for Large Scale Multiprocessors
We present a new multiple ring network for multiprocessors, called the Multistage Ring Network(MRN). The MRN has a 2-level hierarchy of register insertion rings, and its interconn...
Dongho Yoo, Inbum Jung, Seung Ryoul Maeng, Hyungla...