62 search results - page 5 / 13 » An Efficient Fault-Tolerant VLSI Architecture Using Parallel... |
159
click to vote
DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
We consider the implication of deep sub-micron VLSI technology on the design of communication frameworks for parallel DSP systems-on-chip. We assert that distributed data transfer...
161
click to vote
PDP
2010
IEEE
15 years 10 months ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
162
click to vote
TCSV
2002
15 years 6 months ago
2002
This paper presents an efficient VLSI architecture design of MPEG-4 shape coding, which is the key technology for supporting the content-based functionality of the MPEG-4 Video sta...
241
Voted
MM
2005
ACM
16 years 7 hour ago
2005
ACM
Storage and retrieval technology for large-scale medical image systems has matured significantly during the past ten years but many implementations still lack cost-effective backu...
140
Voted
ISCAS
1993
IEEE
15 years 10 months ago
1993
IEEE
– This paper describes an efficient architecture for FIR filters. By exploiting the reduced complexity made possible by the use of sparse powers-of-two coefficients, an FIR ...