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MEMOCODE
2003
IEEE
16 years 16 days ago
LOTOS Code Generation for Model Checking of STBus Based SoC: the STBus interconnect
In the design process of SoC (System on Chip), validation is one of the most critical and costly activity. The main problem for industrial companies like STMicroelectronics, stand...
Pierre Wodey, Geoffrey Camarroque, Fabrice Baray, ...
ICWE
2004
Springer
16 years 19 days ago
Modeling the Structure of Web Applications with ArgoUWE
The UWE methodology provides a systematic, UML-based approach for the development of Web applications. The CASE tool ArgoUWE supports the design phase of the UWE development proces...
Alexander Knapp, Nora Koch, Gefei Zhang
CHI
1995
ACM
15 years 10 months ago
The ScienceWare Modeler: a learner-centered tool for students building models
The Modeler is designed using a learner-centered approach [5], with scaffolding to address the specific needs of learners. Scaffolding [3] is an educational term that refers to pro...
Shari L. Jackson
ENTCS
2008
79views more  ENTCS 2008»
15 years 7 months ago
j-POST: a Java Toolchain for Property-Oriented Software Testing
Abstract. j-POST is an integrated toolchain for property-oriented software testing. This toolchain includes a test designer, a test generator, and a test execution engine. The test...
Yliès Falcone, Laurent Mounier, Jean-Claude...
CORR
2006
Springer
112views Education» more  CORR 2006»
15 years 7 months ago
High-level synthesis under I/O Timing and Memory constraints
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
Philippe Coussy, Gwenolé Corre, Pierre Bome...