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» An improvement in formal verification
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155
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CAV
2004
Springer
111views Hardware» more  CAV 2004»
16 years 3 days ago
Using Interface Refinement to Integrate Formal Verification into the Design Cycle
Jacob Chang, Sergey Berezin, David L. Dill
HASE
2008
IEEE
15 years 6 months ago
Aiding Modular Design and Verification of Safety-Critical Time-Triggered Systems by Use of Executable Formal Specifications
Designing safety-critical systems is a complex process, and especially when the design is carried out at different f abstraction where the correctness of the design at one level i...
Kohei Sakurai, Péter Bokor, Neeraj Suri
DAC
2000
ACM
16 years 7 months ago
Formal verification of iterative algorithms in microprocessors
Contemporary microprocessors implement many iterative algorithms. For example, the front-end of a microprocessor repeatedly fetches and decodes instructions while updating interna...
Mark Aagaard, Robert B. Jones, Roope Kaivola, Kath...
JAVACARD
2000
15 years 10 months ago
Formal Specification and Verification of JavaCard's Application Identifier Class
Abstract This note discusses a verification in PVS of the AID (Application Identifier) class from JavaCard's API. The properties that are verified are formulated in the interf...
Joachim van den Berg, Bart Jacobs, Erik Poll