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CODES
2004
IEEE
15 years 10 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
ICDE
2008
IEEE
153views Database» more  ICDE 2008»
16 years 8 months ago
An Architecture for Query Optimization in Sensor Networks
Ixent Galpin, Christian Y. A. Brenninkmeijer, Farh...
DSD
2008
IEEE
136views Hardware» more  DSD 2008»
16 years 1 months ago
Network Interface Sharing Techniques for Area Optimized NoC Architectures
Although preliminary analysis frameworks point out the performance speed-ups achievable by on-chip networks with respect to state-of-the-art interconnects, the area concern remain...
Alberto Ferrante, Simone Medardoni, Davide Bertozz...