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IPPS
2007
IEEE
16 years 1 months ago
Packet Reordering in Network Processors
Network processors today consists of multiple parallel processors (microengines) with support for multiple threads to exploit packet level parallelism inherent in network workload...
S. Govind, R. Govindarajan, Joy Kuri
ISCA
2003
IEEE
114views Hardware» more  ISCA 2003»
16 years 26 days ago
Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture
This paper describes the polymorphous TRIPS architecture which can be configured for different granularities and types of parallelism. TRIPS contains mechanisms that enable the p...
Karthikeyan Sankaralingam, Ramadass Nagarajan, Hai...
CCGRID
2006
IEEE
15 years 11 months ago
Compilation of XSLT into Dataflow Graphs for Web Service Composition
Our current research into programming models for parallel web services composition is targeted at providing mechanisms for obtaining higher throughput for large scale compute and ...
Peter M. Kelly, Paul D. Coddington, Andrew L. Wend...
ICIP
1997
IEEE
16 years 9 months ago
Model Based Extraction of Articulated Objects in Image Sequences for Gait Analysis
This paper describes an approach to the extraction of articulated objects which will be used for gait analysis. In most medical applications markers are used to determine trajecto...
Dorthe Meyer, Joachim Denzler, Heinrich Niemann
ISSTA
2000
ACM
15 years 12 months ago
Classification schemes to aid in the analysis of real-time systems
This paper presents three sets of classification schemes for processes, properties, and transitions that can be used to assist in the analysis of real-time systems. These classifi...
Paul Z. Kolano, Richard A. Kemmerer