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» Application of Reduce Order Modeling to Time Parallelization
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ISCAS
2006
IEEE
129views Hardware» more  ISCAS 2006»
16 years 1 months ago
Computing during supply voltage switching in DVS enabled real-time processors
In recent times, much attention has been devoted to power optimization for real-time systems, while guaranteeing that such systems meet their hard (or soft) scheduling deadlines. ...
Chunjie Duan, Sunil P. Khatri
ICON
2007
IEEE
16 years 1 months ago
An Approximate Analysis of the Balance among Performance, Utilization and Power Estimation of Server Systems by Use of the Batch
- In this paper we analyze the performance, utilization, and power estimation of server systems by both adopting the batch service and adjusting the batch size. In addition to redu...
Ying-Wen Bai, Yung-Sen Cheng, Cheng-Hung Tsai
SRDS
2003
IEEE
16 years 15 days ago
Buffer Management in Probabilistic Peer-to-Peer Communication Protocols
In multipeer communication decentralised probabilistic protocols have received a lot of attention because of their robustness against faults in the communication traffic and thei...
Boris Koldehofe
LCPC
2007
Springer
16 years 1 months ago
Communicating Multiprocessor-Tasks
The use of multiprocessor tasks (M-tasks) has been shown to be successful for mixed task and data parallel implementations of algorithms from scientific computing. The approach o...
Jörg Dümmler, Thomas Rauber, Gudula R&uu...
FCCM
2007
IEEE
129views VLSI» more  FCCM 2007»
16 years 1 months ago
Automatic On-chip Memory Minimization for Data Reuse
FPGA-based computing engines have become a promising option for the implementation of computationally intensive applications due to high flexibility and parallelism. However, one...
Qiang Liu, George A. Constantinides, Konstantinos ...