3171 search results - page 400 / 635 » Application of Reduce Order Modeling to Time Parallelization |
262
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HPCA
2011
IEEE
14 years 10 months ago
2011
IEEE
In current Chip-multiprocessors (CMPs), a significant portion of the die is consumed by the last-level cache. Until recently, the balance of cache and core space has been primari...
233
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IEEEPACT
2009
IEEE
15 years 4 months ago
2009
IEEE
As the gap between processor and memory continues to grow, memory performance becomes a key performance bottleneck for many applications. Compilers therefore increasingly seek to m...
231
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DSD
2007
IEEE
16 years 1 months ago
2007
IEEE
Developing highly efficient and reliable embedded systems demands hardware/software (HW/SW) co-design and, therefore, co-simulation. In order to be highly configurable, embedded...
230
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UML
2001
Springer
15 years 11 months ago
2001
Springer
The work presented here is part of a project that aims at the definition of a methodology for developing realtime software systems based on UML. In fact, being relatively easy to ...
174
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ICPP
2008
IEEE
16 years 1 months ago
2008
IEEE
The slow speed of conventional execution-driven architecture simulators is a serious impediment to obtaining desirable research productivity. This paper proposes and evaluates a f...