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ICCAD
1996
IEEE
121views Hardware» more  ICCAD 1996»
15 years 11 months ago
Identification of unsettable flip-flops for partial scan and faster ATPG
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...
Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs
RTS
2008
133views more  RTS 2008»
15 years 6 months ago
Non-migratory feasibility and migratory schedulability analysis of multiprocessor real-time systems
Abstract The multiprocessor scheduling of collections of real-time jobs is considered. Sufficient tests are derived for feasibility analysis of a collection of sporadic jobs where ...
Sanjoy K. Baruah, Nathan Fisher
MA
2011
Springer
204views Communications» more  MA 2011»
15 years 2 months ago
Estimating structural VARMA models with uncorrelated but non-independent error terms
The asymptotic properties of the quasi-maximum likelihood estimator (QMLE) of vector autoregressive moving-average (VARMA) models are derived under the assumption that the errors ...
Y. Boubacar Mainassara, Christian Francq
ICCAD
2002
IEEE
85views Hardware» more  ICCAD 2002»
16 years 4 days ago
On undetectable faults in partial scan circuits
We study the undetectable faults in partial scan circuits under a test application scheme referred to as transparent-scan. The transparent-scan approach allows very aggressive tes...
Irith Pomeranz, Sudhakar M. Reddy
ASPDAC
2000
ACM
96views Hardware» more  ASPDAC 2000»
15 years 10 months ago
A programmable built-in self-test core for embedded memories
Testing embedded memories is becoming an industry-wide concern with the advent of deep-submicron technology and system-on-chip applications. We present a prototype chip for a progr...
Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu