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ACSC
2005
IEEE
16 years 1 months ago
Large Object Segmentation with Region Priority Rendering
The Address Recalculation Pipeline is a hardware architecture designed to reduce the end-to-end latency suffered by immersive Head Mounted Display virtual reality systems. A deman...
Yang-Wai Chow, Ronald Pose, Matthew Regan
APCSAC
2005
IEEE
16 years 1 months ago
Irregular Redistribution Scheduling by Partitioning Messages
Abstract. Dynamic data redistribution enhances data locality and improves algorithm performance for numerous scientific problems on distributed memory multi-computers systems. Prev...
Chang Yu, Ching-Hsien Hsu, Kun-Ming Yu, Chiu-Kuo L...
CODES
2005
IEEE
16 years 1 months ago
System-level design automation tools for digital microfluidic biochips
Biochips based on digital microfluidics offer a powerful platform for massively parallel biochemical analysis such as clinical diagnosis and DNA sequencing. Current full-custom de...
Krishnendu Chakrabarty, Fei Su
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DSN
2005
IEEE
16 years 1 months ago
Reversible Fault-Tolerant Logic
It is now widely accepted that the CMOS technology implementing irreversible logic will hit a scaling limit beyond 2016, and that the increased power dissipation is a major limiti...
P. Oscar Boykin, Vwani P. Roychowdhury
GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
16 years 1 months ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed
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