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MICRO
1997
IEEE
105views Hardware» more  MICRO 1997»
15 years 11 months ago
The Multicluster Architecture: Reducing Cycle Time Through Partitioning
The multicluster architecture that we introduce offers a decentralized, dynamically-scheduled architecture, in which the register files, dispatch queue, and functional units of t...
Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvon...
ICCAD
1994
IEEE
106views Hardware» more  ICCAD 1994»
15 years 11 months ago
On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution
Several industrial FPGA routing architectures have been shown to have no efficient routing algorithms (unless P=NP) [3,4]. Here, we further investigate if the intractability of th...
Yu-Liang Wu, Douglas Chang
CIT
2007
Springer
15 years 10 months ago
An Aspect Enhanced Method of NFR Modeling in Software Architecture
Existence of crosscutting concerns in software requirements often intensifies complexity of software development. Modeling and analysis of these concerns at software architecture ...
Hamid Bagheri, Seyed-Hassan Mirian-Hosseinabadi, H...
DAC
2007
ACM
15 years 10 months ago
A Framework for the Validation of Processor Architecture Compliance
We present a framework for validating the compliance of a design with a given architecture. Our approach is centered on the concept of misinterpretations. These include missing be...
Allon Adir, Sigal Asaf, Laurent Fournier, Itai Jae...
DATE
2004
IEEE
109views Hardware» more  DATE 2004»
15 years 10 months ago
RTL Processor Synthesis for Architecture Exploration and Implementation
Architecture description languages are widely used to perform architecture exploration for application-driven designs, whereas the RT-level is the commonly accepted level for hard...
Oliver Schliebusch, Anupam Chattopadhyay, Rainer L...