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JUCS
2000
120views more  JUCS 2000»
15 years 6 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
DAC
2005
ACM
16 years 8 months ago
High performance encryption cores for 3G networks
This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the conf...
René Cumplido, Tomás Balderas-Contre...
ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
16 years 3 months ago
Performance Efficiency of Context-Flow System-on-Chip Platform
Recent efforts in adapting computer networks into system-on-chip (SOC), or network-on-chip, present a setback to the traditional computer systems for the lack of effective program...
Rami Beidas, Jianwen Zhu
DAC
2009
ACM
16 years 1 months ago
PDRAM: a hybrid PRAM and DRAM main memory system
In this paper, we propose PDRAM, a novel energy efficient main memory architecture based on phase change random access memory (PRAM) and DRAM. The paper explores the challenges i...
Gaurav Dhiman, Raid Ayoub, Tajana Rosing
SAINT
2009
IEEE
16 years 1 months ago
Davis Social Links: Leveraging Social Networks for Future Internet Communication
In this paper, we present a social network based network communication architecture, Davis Social Links (DSL). DSL uses the trust and relationships inherent to human social networ...
Lerone Banks, Prantik Bhattacharyya, Matthew Spear...