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VLSID
2001
IEEE
118views VLSI» more  VLSID 2001»
16 years 7 months ago
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language
Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizationsfor programmable systems assumed a fixed cache hierarchy. Withthe wideningproce...
Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexand...
ICSE
2004
IEEE-ACM
16 years 7 months ago
The Dublo Architecture Pattern for Smooth Migration of Business Information Systems: An Experience Report
While the importance of multi-tier architectures for enterprise information systems is widely accepted and their benefits are well published, the systematic migration from monolit...
Wilhelm Hasselbring, Ralf Reussner, Holger Jaekel,...
ICSE
2008
IEEE-ACM
16 years 7 months ago
Performance modeling for service oriented architectures
We present a tool for performance modeling of Service Oriented Architectures (SOAs). As mission-critical use of whole-ofgovernment SOAs become pervasive, the capability to model a...
Paul Brebner
ICCAD
2003
IEEE
175views Hardware» more  ICCAD 2003»
16 years 3 months ago
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous design, this requires the consideration o...
Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhi...